`include "CP0Defines.svh"
`include "defines.svh"
module ID_EXE ( 
    input logic clk,
    input logic reset,

    input logic ID_EXE_Flush, 
    input logic ID_EXE_Stall,

    input logic [31:0]ID_PC,
    input logic [31:0]ID_NPC,
    input logic [31:0]ID_Instr,
    input logic [4:0]ID_ALUOp,
    input logic ID_DMWr,
    input logic ID_ALU_DataA_Sig,
    input logic ID_ALU_DataB_Sig,
    input logic [2:0]ID_Reg_Writed,
    input logic [2:0]ID_DMOp,
    input logic ID_MemToRegWr,
    input logic [1:0]ID_Data_To_Reg_Sel,
    input logic [31:0]ID_Imm_32,
    input logic [31:0]ID_Rs_Data,
    input logic [31:0]ID_Rt_Data,
    input logic [4:0]ID_RW,
    input logic ID_IsBranch,
    input logic ID_Immjump,
    input logic ID_CP0Wr,
    input logic ID_DMRd,
    input logic [4:0] ID_Rs,
    input logic [4:0] ID_Rt,
    input ExceptionType ID_ExceptionTypeEnd,
    input PredictResult ID_PredictResult,

    output logic [31:0]EXE_PC,
    output logic [31:0]EXE_NPC,
    output logic [31:0]EXE_Instr, 
    output logic [4:0]EXE_ALUOp,
    output logic EXE_DMWr,
    output logic EXE_ALU_DataA_Sig,
    output logic EXE_ALU_DataB_Sig,
    output logic [2:0]EXE_Reg_Writed,
    output logic [2:0]EXE_DMOp,
    output logic EXE_MemToRegWr,
    output logic [1:0]EXE_Data_To_Reg_Sel,
    output logic [31:0]EXE_Imm_32, 
    output logic [31:0]EXE_Rs_Data,
    output logic [31:0]EXE_Rt_Data,
    output logic [4:0]EXE_RW,
    output logic EXE_IsBranch,
    output logic EXE_Immjump,
    output logic EXE_CP0Wr,
    output logic EXE_DMRd,
    output logic [4:0] EXE_Rs,
    output logic [4:0] EXE_Rt,
    output ExceptionType EXE_ExceptionType,
    output PredictResult EXE_PredictResult
);
    always_ff @(posedge clk,negedge reset)
    begin
        if(!reset || ID_EXE_Flush)begin
            EXE_PC <= 32'b0;
            EXE_NPC <= 32'b0;
            EXE_Instr <= 32'b0;
            EXE_ALUOp <= 5'b0;
            EXE_DMWr <= 1'b0;
            EXE_ALU_DataA_Sig <= 1'b0;
            EXE_ALU_DataB_Sig <= 1'b0;
            EXE_Reg_Writed <= 3'b0;
            EXE_DMOp <= 3'b0;
            EXE_MemToRegWr <= 1'b0;
            EXE_Data_To_Reg_Sel <= 2'b0;
            EXE_Imm_32 <= 32'b0;
            EXE_Rs_Data <= 32'b0;
            EXE_Rt_Data <= 32'b0;
            EXE_RW <= 5'b0;
            EXE_IsBranch<=1'b0;
            EXE_Immjump<=1'b0;
            EXE_CP0Wr<=1'b0;
            EXE_DMRd<=1'b0;
            EXE_Rs<=5'b0;
            EXE_Rt<=5'b0;
            EXE_ExceptionType<=`NoException;
            EXE_PredictResult<='0;
        end    
        else if(!ID_EXE_Stall)begin
            EXE_PC <= ID_PC;
            EXE_NPC <= ID_NPC;
            EXE_Instr <= ID_Instr;
            EXE_ALUOp <= ID_ALUOp;
            EXE_DMWr <= ID_DMWr;
            EXE_ALU_DataA_Sig <= ID_ALU_DataA_Sig;
            EXE_ALU_DataB_Sig <= ID_ALU_DataB_Sig;
            EXE_Reg_Writed <= ID_Reg_Writed;
            EXE_DMOp <= ID_DMOp;
            EXE_MemToRegWr <= ID_MemToRegWr;
            EXE_Data_To_Reg_Sel <= ID_Data_To_Reg_Sel;
            EXE_Imm_32 <= ID_Imm_32;
            EXE_Rs_Data <= ID_Rs_Data;
            EXE_Rt_Data <= ID_Rt_Data;
            EXE_RW <= ID_RW;
            EXE_IsBranch<=ID_IsBranch;
            EXE_Immjump<=ID_Immjump;
            EXE_CP0Wr<=ID_CP0Wr;
            EXE_DMRd<=ID_DMRd;
            EXE_Rs<=ID_Rs;
            EXE_Rt<=ID_Rt;
            EXE_ExceptionType<=ID_ExceptionTypeEnd;
            EXE_PredictResult<=ID_PredictResult;
        end
        else 
            ;
    end
endmodule